High Speed Viterbi Decoder Design With A Rate Of 1⁄2 Convolution Code For Tcm Systems

High speed Viterbi decoder design for trellis coded modulation (TCM) is presented in this paper. It is well known that the Viterbi decoder (VD) is the dominant module for determining shortest path. We propose a pre-computation architecture incorporated with T-algorithm for VD, which can find the shortest path without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-1/2 convolution code used in a TCM system shows that compared with the full trellis VD, with the constraint length 9. This work focuses on the realization of convolution encoder and adaptive Viterbi decoder (AVD) with a constraint length (K) of 9 and a code rate (k/n) of 1⁄2, Implemented on FPGA. The results are tested by using ISE 10.1 and Modelsim.